1. Field of the Invention
The present invention generally relates to data processing systems such as central processing units (hereinafter, referred to CPUs), and more particularly to a general-purpose register group circuit used in the data processing systems.
2. Description of the Prior Art
Conventionally, data processing systems such as CPUs are equipped with a general-purpose register group circuit comprised of a plurality of groups of registers. The general-purpose register group circuit is used to hold data used for one or a plurality of data operations or address operations and the results of such operations. The general-purpose register group circuit is connected to a plurality of buses within the CPU.
FIG. 1 shows a prior art of a conventional general-purpose register group circuit, which includes four general-purpose register groups 10 through 13, each of the register groups having four four-bit registers. The register groups 10 through 13 are connected to internal buses 20, 21 and 22 (these reference numbers are omitted from FIG. 1 for the sake of convenience). The internal bus 20 has bus lines 20a, 20b, 20c and 20d, and the internal bus 21 has bus lines 21a, 2lb, 21c and 21d. Further, the internal bus 22 has bus lines 22a, 22b, 22c and 22d.
More particularly, data is supplied to the register groups 10-13 via the internal bus 20, and data from the register groups 10-13 are supplied to ether the internal bus 21 or 22. The data can be latched in each of the register groups 10-13 in response to respective register control signals. More particularly, these register control signals include register input control signals RdxLT.sub.-- P and RxLT.sub.-- N where X is the identification number of the register groups. For example, the register group 10 latches data supplied via the internal bus 20 in response to the register input control signals ROLT.sub.-- P and ROLT.sub.-- N. The data from the register groups 10-13 can be read therefrom for each register group in response to register output control signals. More particularly, these register output control signals include register output control signals RxB and RxC where x is the identification number of the register groups. For example, data is read from the register group 10 and output to the internal bus 21 or 22 in response to the register output control signals ROB and ROC.
FIGS. 2 and 3 are block diagrams of a one-bit circuit of each register provided in each of the register groups 10-13 (hereinafter such as circuit is referred to as a unit register). The symbols CK.sub.-- P, CK.sub.-- N, D, RB, RC, BOUT and COUT shown in FIG. 1 correspond to corresponding terminals shown in FIGS. 2 and 3. The unit register shown in FIG. 2 is comprised of a latch unit 30 and an output unit 40. Similarly, the unit register shown in FIG. 3 is comprised of the same latch unit 30 and an output unit 50. That is, the structure of the output unit 40 shown in FIG. 2 differs from that of the output unit 50 shown in FIG. 3.
More particularly, the output unit 40 of the unit register shown in FIG. 2 includes inverters 41 and transmission gates 42. In order to control the transmission gates 42, the output unit 40 needs, for one internal bus, for example, the internal bus 21, the register output control signals RxLT.sub.-- P and RxLT.sub.-- N respectively applied to the terminals RB.sub.-- P and RB.sub.-- N as well as the register output control signals RxB, and RxC respectively applied to the terminals RC.sub.-- P and RC.sub.-- N.
The output unit 50 of the unit register shown in FIG. 3 includes two-input NAND gates 51 and two tri-state gates 52. In order to control the tri-state gates 52, the output unit 50 needs, for one internal bus, for example, the internal bus 21, the register output control signals RB and RC. Regarding the register output control signals, the circuit configuration shown in FIG. 3 is advantageous over that shown in FIG. 2 because the number of control signals necessary for the circuit configuration shown in FIG. 3 is less than that used in the circuit configuration shown in FIG. 2. One inverter 41 and one transmission gate 42 shown in FIG. 2 needs four transistors, while one NAND gate 51 and one tri-state gate 52 needs seven transistors. In this regard, the circuit configuration shown in FIG. 3 is advantageous over that shown in FIG. 2.
In common with the circuits shown in FIGS. 2 and 3, each unit register directly sends data to the internal bus 21 or 22, to which a number of unit registers are connected. Hence, each internal bus has a heavy load. With the above in mind, each unit register is designed to have transistors of a large size to drive the internal bus having a heavy load. However, the larger the number of unit registers, the greater the chip area occupied by the general-purpose register group circuit.
In the unit register shown in FIG. 3, it is possible to perform the data read and write operations within the same machine cycle. Referring to FIG. 4, when the control signal RxLT.sub.-- P supplied to the terminal CK.sub.-- P is switched to the high level (H), and the register output control signal RB is switched to the high level, data from the internal bus 20 can be latched and data can be sent to the internal bus 21 within the same machine cycle. However, in this case, the data passes through a path indicated by the thick solid line shown in FIG. 4. Hence, as shown in FIG. 5, the data is output to the internal bus 21 with a time delay of A.